Course           Nano VLSI and Design Fundamentals (Basic VLSI Level 1)
Category        Full length Certified Course
Duration         8 weeks (52 hours)
Timings          6.30pm to 8.30pm
Frequency     M-W-F (inclusive of Theory and Labs)
Eligibility        FE/SE/TE/Diploma/BE/BTech/ME/MTech/MS

"Basic Nano VLSI Design Key features"

Course Description :
• The course lays the foundation for state-of-the-art CMOS design. It emphasizes with the basics of design and layout of CMOS VLSI circuits as well as study the essential physics required for understanding of VLSI circuits and VLSI design rules. The course includes the study of the MOS device, critical interconnect and gate characteristics that determine the performance of VLSI circuits. It also includes CMOS logic design from transistor level schematic to layout. Learn concepts like process scaling and reliability.

Course Outline with objectives:

• Solid state Electronics fundamentals for Conductor, Semiconductor and Insulators, Fermi Level, and other    semiconductor physics.

• MOSFET Threshold voltage, flat band condition, threshold adjustment, linear and saturated operation, FET   capacitance mobility saturation and thermal variations, Short channel effect and hot electron effects
  electromigration, Aluminum spikes and contact resistance.

• Silicon gate NMOS CMOS process, silicon patterning, mask generation, active area definition, transistor    formation contacts, metallization, chip packaging process limitations scaling factor of MOS circuits, scaling,   functional limitations of scaling, scaling of wires and interconnections, latch up in scaled CMOS circuits,   device reliability, soft errors, noise margins, lead inductance, gate oxide reliability, polysilicon resistance    and input protection.

• Course takes through Historic, Medieval and Modern semiconductor flow in CMOS IC design.

• The purpose of design rules, NMOS rules, CMOS design rules, passive load NMOS inverter, active load    NMOS inverter, NMOS NAND & NOR gates, CMOS inverter, CMOS NAND & NOR gates, interlayer contacts

• MOSFET aspect and inverter ratio, enhancement & depletion mode pull ups, enhancement Vs depletion   mode pull ups, standard CMOS inverter, NMOS threshold voltage and inverter ratio transit and switching    speed of NMOS & CMOS inverter

• CMOS & steering logic, RC delay lines, CMOS gates, dynamic ratio-less inverter with large capacitive buffer    load, designing pass transistor logic. Dynamic CMOS design.


Text Books:
1. Introduction to VLSI Design, E.D.Fabricius, 1990.
2. Principles of CMOS VLSI Design a System Perspective, Neil H.E.Weste, Kamran Eshraghian,
    Addison-Wesley, 2005.
3. Basic VLSI Design, D. A. Pucknell, Kamran Eshraghian, Prentice Hall. Publication year 2010 3rd edition